Currently, a typical power semiconductor device usually combines metal oxide semiconductor field effect transistors (MOSFETs) and an integrated circuit (IC) controller in one package to reduce number of peripheral devices and improve the utilization efficiency of power supplies and other components. For a double diffused metal oxide semiconductor field effect transistor (DMOSFET) having a source on its top surface, the top source of the chip usually is connected to an exposed die paddle of a lead frame and thus is grounded.
To achieve the above said package structure, the chip has to be flipped and attached to the lead frame die paddle, which will face some difficulties, such as the optimization of the size and simplification of the shape of the exposed die paddle of lead frame, the achievement of the connection between the chip source and the die paddle to optimize heat dissipation, and the achievement of a good interconnection between the gate on top of the chip and the IC controller for such a flip chip configuration.
A specific existing semiconductor device package as shown in FIG. 1 is made according to the circuit diagram in FIG. 2, which contains a P-type high-side (HS) MOSFET, a N-type low-side (LS) MOSFET and an IC controller that are installed on one lead frame. The installation space of the package limits the size of the HS MOSFET, LS MOSFET and IC controller, which have a great impact on the improvement of performance of power semiconductor device.
However, in the above package structure, electrodes on top surface of the LS MOSFET connect to the HS MOSFET, the IC controller or external components directly through bonding wires, which may be connected to the same pin. Therefore, it is difficult to install a flip chip to connect the source on its top surface with the die paddle, and it is impossible to make the exposed die paddle as electrode ground and to improve the heat dissipation effect.